1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor memory device and, more particularly, to a method for forming trench isolation regions of different depths.
2. Description of the Prior Art
A NAND type flash memory device has a plurality of memory cells connected in series, with one common diffusion layer. Therefore, the plurality of memory cells share one input/output line (bit line) and contact.
The NAND type flash memory device has several disadvantages; the random read speed is slower than a NOR type flash memory device and data programming and erasing are performed in a single unit comprising a plurality of cells connected in series to NAND cell array. However, the advantage of the NAND type flash memory device is the small cell area, which lowers the production cost per bit.
Recently, in the NAND type flash memory device, there is an attempt to deepen silicon etching depth, targeted to shallow trench isolation (STI), to 8000 xc3x85. This method is referred to as deep trench isolation (DTI).
The conventional DTI method for fabricating semiconductor memory devices will be described with reference to annexed drawings FIGS. 1A to 1D.
Referring to FIG. 1A, an STI formation region and a DTI formation region are defined on a semiconductor substrate 10. On the surface of the semiconductor substrate 10, a first insulating layer 11, a second insulating layer 12 and a third insulation layer 13 are sequentially deposited. The first insulating layer 11 is a pad oxide layer, the second insulating layer 12 is a pad nitride layer, and the third insulating layer 13 is an oxide hard mask layer. Subsequently, a first photoresist 14 is deposited on the third insulating layer 13 and is exposed and developed to selectively pattern the photoresist.
Referring to FIG. 1B, the first insulating layer 11, the second insulating layer 12, the third insulating layer 13 and the semiconductor substrate 10 are selectively etched off by using the patterned first photoresist 14 as a mask, thereby forming a plurality of STI regions 15a, 15b. The STI regions 15a, 15b have a depth of 2500xcx9c3000 xc3x85 from the surface of the semiconductor substrate 10.
Referring to FIG. 1C, the patterned first photoresist 14 is removed and a second photoresist 16 is deposited and selectively patterned by exposure and development processes to expose a DTI formation region. The second photoresist 16 has a thickness of 1xcx9c3 xcexcm.
Referring to FIG. 1D, the STI region of 15b of the semiconductor substrate 10 is etched more deeply by using the patterned second photoresist 16 and the third insulating layer 13 as a mask, thereby forming a DTI region 17. The DTI region 17 has a depth of 7000xcx9c8000 xc3x85 from the surface of the semiconductor substrate 10.
As described above, the conventional DTI process requires additional steps to form the hard mask 13 and the DTI region 17 compared to the conventional STI process. Here, the photoresist has insufficient etch selectivity (0.9:1) relative to silicon. Therefore, the second photoresist 16 is etched off in silicon etch process to form the DTI region 17. As a result, the STI region is damaged, thereby causing poor operation of the semiconductor device as shown in a SEM photograph of FIG. 2. In order to prevent this problem, the third insulating layer 13 is employed as a hard mask in the conventional DTI process.
However, the third insulating layer 13 is additionally formed regardless of the original purpose, thereby complicating the fabrication process and increasing the production cost. Moreover, interfacial disharmony between the third insulating layer 13 and the photoresist 14 and 16 cause pattern collapse, as shown in FIG. 3.
In addition, the photoresist must have a predetermined thickness, approximately 1xcx9c3 xcexcm, in order to etch the DTI region 17. Therefore, it has a disadvantage of reducing process margin when performing the mask process.
Therefore, the present invention has been made to solve the above problems. An object of the present invention is to provide a method for fabricating a semiconductor memory device capable of simplifying formation process of trench isolation regions with different depths and increasing mask process margin.
In order to accomplish the above object, the present invention provides a method for fabricating a semiconductor memory device with a photoresist of increased etch selectivity by changing the physical properties of the photoresist in forming trench isolation regions with different depths.
The present invention comprises the steps of: depositing first and second insulating layers on a semiconductor substrate where (STI) regions and (DTI) regions are defined, forming the STI region by selectively etching the second and first insulating layers and the semiconductor substrate, forming a photoresist to cover the STI region and curing the surface thereof, and forming the DTI region by using the cured photoresist and the second insulating layer as a mask.
In the present invention, the curing step of the photoresist surface may include the high energy implantation of argon ions into the photoresist, preferably by employing an e-beam curing process. Furthermore, the implanted concentration of argon ions may be 1012xcx9c15 cm3, the ion implantation energy may be 10xcx9c200 KeV, and the energy of the e-beam curing process may be 1000xcx9c2000 uC/cm2.